1. Field of the Invention
The present invention relates to a cache system to be provided between a processor and a memory device.
2. Description of the Related Art
Unlike ordinary processors, any processor that processes streams, such as 3D-graphics large-scale integration (LSI) processor, performs no branching. Therefore, the pipeline process would not be disturbed.
In most cases where such an LSI processor refers to the data stored in a memory, it first pre-fetches desired data from the memory and then fetches the data from the memory after the data is filled in a cache system by virtue of the pre-fetching. The latency of the memory is thereby concealed.
The cache system needs to have a complicated circuit for determining hits in pre-fetching desired data and fetching the data, as will be described below.
First, the processor such as an LSI (requester) supplies a read address to a tag unit and the FIFO memory unit, both provided in the cache system. The tag unit is constituted by a table stored in the memory. It holds the address at which the data is stored in a cache-data storage unit and the addresses at which data items are stored in the memory. The determining unit of the cache system refers to the tag unit, determining whether a cache-data storage unit contains the data of the address read from processor (it determines whether a hit has been made). This operation is called “pre-fetching.”
If the data of the address is not stored in the cache-data storage unit, a signal indicating this fact is supplied to the refill-processing unit of the cache system. On receiving the signal, the refill-processing unit outputs a read address and a refill request to the memory. In response to the refill request, the memory supplies the data of the read address to the cache-data storage unit (it performs refilling).
Upon lapse of a predetermined time, an FIFO memory unit supplies the read address to the determining unit. The determining unit determines again whether or not a hit has been made. This operation is called “fetching.” If the cache-data storage unit stores the data of the read address, this data is supplied to the requester.
As indicated above, the determining unit determines whether a hit has been made, in the pre-fetching and the fetching. Therefore, the determining unit must have a circuit configuration that can perform hit-determination in both the pre-fetching and the fetching. The determining unit inevitably has a large area. A number of request are made to the cache system, particularly in 3D-graphics processes. To cope with this, the determining unit has a very large area.